The present invention relates generally to a method and apparatus for integrated circuit burn-in, and more specifically to a method and apparatus for wafer level burn-in before dice are packaged into individual circuit chips.
The advance of semiconductor technology in recent years has greatly increased the density of a semiconductor device. In order to satisfy the strong market demand of highly portable and compact electronic gadgets, many semiconductor manufacturers are dedicated to the fabrication of integrated circuits with densely populated semiconductor devices, a large number of input/output (I/O) terminals and fast processing speed. After the fabrication of integrated circuits on a wafer, each die on the wafer needs to be properly tested and packaged to prevent it from being damaged by moisture or external forces.
As the number of I/O pins and the processing speed of a circuit device increase, the technology of packaging the die becomes more and more critical. How to package a large number of pins in a small volume and maintain the high processing speed of the device have to be carefully considered. In addition, the issue of heat dissipation from the high density circuit must be addressed. After each die is packaged, the circuit on the die has to be tested to ensure that it functions properly as designed.
One important step in the conventional test procedures is burn-in. In the conventional packaging technology, a wafer is first sawed and dice are cut from the wafer for packaging. Each die is sealed and packaged as an integrated circuit chip in a package such as TSOP, SOJ, QFP and BGA, . . . , etc. The integrated circuit is then under burn-in on a test socket separately. Different test sockets are required for the burn-in of the devices that have different types of packages. The purpose of the burn-in process is to identify and remove the devices that suffer from infant mortality.
With the conventional technology, the process of burn-in usually takes 8 to 96 hours and requires a specific burn-in system for a given integrated circuit chip. The technology relies on a burn-in system that sends signals to directly control the integrated circuit. During a test cycle, 50% of the duty cycle is used and only one address bit can be controlled. Most of the test uses write cycle only. Because of the inefficiency, a packaged integrated circuit spends a long time on a burn-in board between loading and off-loading.
There are other drawbacks in the conventional burn-in technology. The pins of the circuit sometimes are bent to cause a problem. Both the burn-in boards and the socket have short life. In addition, if wafer process results in defects found in the packaged integrated circuit under burn-in, the problem is uncovered only after many integrated circuits have been packaged and many wafers have been manufactured. Therefore, there is a strong demand in having a better burn-in technology that can uncover the defects and reflect the wafer process problem as early as possible to reduce the cost and risk.
The present invention has been made to overcome the above-mentioned drawbacks of conventional techniques for the burn-in of integrated circuit chips. The primary object of the invention is to reduce the time required in the burn-in. Accordingly, a method of wafer level burn-in before dice are packaged is provided to speed up the burn-in process and reduce the burn-in time.
Another object of the invention is to provide a burn-in circuit that can be built in an integrated circuit to facilitate the wafer level burn-in method. The built-in burn-in circuit of the invention comprises a main burn-in control circuit, a word-line control circuit and a bit-line control circuit. In addition, internal probing pads are also built in the integrated circuit for providing voltages required to stress the gate oxide or capacitor oxide of a memory cell.
It is also an object of the invention to provide a burn-in test system for the wafer level burn-in of integrated chips. The burn-in test system comprises a plurality of programmable power suppliers and a plurality of programmable relays for providing voltages and control signals for the wafer level burn-in of integrated circuit chips. Control pins provide control signals to all dice under burn-in. Power pins provide voltage signals to each individual die. Each die can be turned on or off separately according to the requirement.
It is yet another object of the invention to provide a wafer level burn-in system comprising a PC, a burn-in test system, a membrane or micro spring probe card and a prober. According to the invention, the burn-in test system is controlled by the PC that provides user interface. The prober provides an automatic station with a hot chuck. The membrane or micro spring probe card connected to the burn-in test system is used to perform the burn-in of a die. Wafers are automatically loaded and aligned by the prober before the burn-in starts.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from a careful reading of a detailed description provided herein below, with appropriate reference to the accompanying drawings.